This invention relates to a process for fabricating semiconductor integrated circuit devices capable of high packing density and high-speed operation.
Emitter-coupled logic (ECL) bipolar semiconductor integrated circuit devices, also known as current-mode logic (CML) devices, have commonly been used in semiconductor integrated circuit application fields requiring especially high speed. In an ECL or CML circuit, for a given power consumption and logic swing, the propagation delay time is mainly determined by the parasitic capacitance of the circuit elements and interconnection wiring, and the base resistance and gainbandwidth product of the transistors. To reduce parasitic capacitance, in particular the base-collector junction capacitance of transistors which make a large contribution to operating speed, it is customary to use polysilicon to lead the base electrode outside the element region thereby to reduce the base region, and to form the polysilicon resistors and metal interconnections on a thick isolation oxide.
To reduce the base resistance, it is necessary to reduce the resistance of the inactive base layer, dispose it as close as possible to the emitter, reduce the width of the emitter, and reduce the resistance of the active base layer under the emitter. Means of improving the gainbandwidth product include making the base and emitter junctions shallow and the epitaxial collector layer thin.
A fabrication process that has been proposed to achieve these goals is described in Japanese Patent Application Publication No. 131698/1986 and a corresponding U.S. patent application Ser. No. 057,510 filed June 3, 1987, now U.S. Pat. No. 4,735,912.
The steps in this fabrication process are illustrated in FIG. 2A to FIG. 2E, which trace the formation of the cross section of a transistor with a double-base structure, in which base electrodes are located on both sides of the emitter to reduce the base resistance. FIG. 2A shows the state after oxide isolation process has been carried out and the polysilicon and selective oxidation mask have been formed. The parts labeled are a P.sup.- type silicon substrate 1, an N.sup.+ -type buried layer 2, an N.sup.- -type epitaxial layer 3, an isolation oxide layer 4, an N.sup.+ -type region 5 for reducing the collector resistance, the polysilicon 6, a nitride film 7 that will become the selective oxidation mask, and a boron-doped layer 8 formed using the nitride film 7 and its patterning resist (not shown in the drawing) as a mask. The polysilicon 6 is selectively oxidized and the nitride film 7 is removed, then the surface of the remaining polysilicon 6 is oxidized, giving the structure shown in FIG. 2B. In this structure the electrodes of the transistor are formed by the polysilicon regions 6a to 6d, which are isolated from one another by an oxide film 9. The boron-doped layer 8 is diffused by heat treatment during this process and becomes a moderate-doped p-type layer forming part of the inactive base. Next, using a resist not shown in the drawing, a high-dosage implant of boron ions is performed on the polysilicon regions 6a and 6c that will become the base electrodes. After the resist is removed, the entire surface is given a low-dosage boron ion implant.
This is followed by heat treatment in a non-oxidizing atmosphere, forming a heavily-doped inactive base 10 and an active base 11 by diffusion from the polysilicon as shown in FIG. 2C. These base regions 10 and 11 are linked by the region 8, which is doped at a moderate concentration. Next contact holes are opened as in FIG. 2C and a slight oxidation is performed on the polysilicon exposed at the contact holes as shown in FIG. 2D. Then, using a mask not shown in the drawings, arsenic ions are implanted into the polysilicon regions 6b and 6d and heat treatment is performed to form the emitter 12. Next the thin oxide is removed and metal electrodes 13a to 13d are formed. With this process it is possible to form shallow junctions of the active base 11 and the emitter 12 and obtain a fairly high-performance transistor.
It is not possible, however, to reduce the base resistance as much as desired because the heavily-doped inactive base 10 and the emitter 12 are separated by the moderately-doped base 8, and resistance in this region cannot be made adequately low. Furthermore, the heat treatment in the selective oxidation of the polysilicon extends the moderately-doped base 8 under the emitter 12, narrowing the active base 11. This leads to considerable recombination of the carriers injected into the base from the emitter, making it difficult to increase the current gain. This tendency worsens at reduced feature sizes, imposing a limit on the shrinkage of the transistor geometry. Also, since the moderately doped base 8 has a deep junction, there are limits to the thinning of the epitaxial layer, creating an obstacle to improvement of the gain-bandwidth product. All of the problems described above can be ascribed to the moderately-doped base 8.